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LTC1285/LTC1288 3V Micropower Sampling 12-Bit A/D Converters in SO-8 Packages DESCRIPTION
The LTC(R)1285/LTC1288 are 3V micropower, 12-bit, successive approximation sampling A/D converters. They typically draw only 160A of supply current when converting and automatically power down to a typical supply current of 1nA whenever they are not performing conversions. They are packaged in 8-pin SO packages and operate on 3V to 6V supplies. These 12-bit, switchedcapacitor, successive approximation ADCs include sample-and-holds. The LTC1285 has a single differential analog input. The LTC1288 offers a software selectable 2-channel MUX. On-chip serial ports allow efficient data transfer to a wide range of microprocessors and microcontrollers over three wires. This, coupled with micropower consumption, makes remote location possible and facilitates transmitting data through isolation barriers. These circuits can be used in ratiometric applications or with an external reference. The high impedance analog inputs and the ability to operate with reduced spans (to 1.5V full scale) allow direct connection to sensors and transducers in many applications, eliminating the need for gain stages.
, LTC and LT are registered trademarks of Linear Technology Corporation.
FEATURES
s s s s s s s s s s s s
s
12-Bit Resolution 8-Pin SO Plastic Package Low Cost Low Supply Current: 160A Typ Auto Shutdown to 1nA Typ Guaranteed 3/4LSB Max DNL Single Supply 3V to 6V Operation Differential Inputs (LTC1285) 2-Channel MUX (LTC1288) On-Chip Sample-and-Hold 100s Conversion Time Sampling Rates: 7.5ksps (LTC1285) 6.6ksps (LTC1288) I/O Compatible with SPI, Microwire, etc.
APPLICATIONS
s s s s s s
Pen Screen Digitizing Battery-Operated Systems Remote Data Acquisition Isolated Data Acquisition Battery Monitoring Temperature Measurement
TYPICAL APPLICATIONS N
12W, S0-8 Package, 12-Bit ADC Samples at 200Hz and Runs Off a 3V Supply
1F 3V
Supply Current vs Sample Rate
1000 TA = 25C VCC = 2.7V VREF = 2.5V fCLK = 120kHz 100
MPU (e.g., 8051) 1 2 VREF +IN VCC CLK 8 7 P1.4 P1.3 P1.2 SERIAL DATA LINK
LTC1285/88 * TA01
SUPPLY CURRENT (A)
10
ANALOG INPUT LTC1285 6 0V TO 3V RANGE 3 -IN DOUT 4 5 CS/SHDN GND
1 0.1 1 10 SAMPLE FREQUENCY (kHz) 100
U
U
U
LTC1285/88 * TA02
1
LTC1285/LTC1288
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VCC) to GND ................................... 12V Voltage Analog and Reference ................ -0.3V to VCC + 0.3V Digital Inputs......................................... -0.3V to 12V Digital Output ............................. -0.3V to VCC + 0.3V
PACKAGE/ORDER INFORMATION
TOP VIEW VREF 1 +IN 2 -IN 3 GND 4 N8 PACKAGE 8-LEAD PDIP 8 7 6 5 VCC CLK DOUT CS/SHDN
ORDER PART NUMBER LTC1285CN8
TJMAX = 150C, JA = 130C/W
TOP VIEW CS/SHDN 1 CH0 2 CH1 3 GND 4 N8 PACKAGE 8-LEAD PDIP
TJMAX = 150C, JA = 130C/W
8 7 6 5
VCC (VREF) CLK DOUT DIN
ORDER PART NUMBER LTC1288CN8
Consult factory for Industrial and Military grade parts.
RECOM ENDED OPERATING CONDITIONS
SYMBOL VCC fCLK tCYC thDI tsuCS tsuDI tWHCLK tWLCLK tWHCS tWLCS PARAMETER Supply Voltage (Note 3) Clock Frequency Total Cycle Time Hold Time, DIN After CLK Setup Time CS Before First CLK (See Operating Sequence) Setup Time, DIN Stable Before CLK CLK High Time CLK Low Time CS High Time Between Data Transfer Cycles CS Low Time During Data Transfer CONDITIONS LTC1285 LTC1288 VCC = 2.7V LTC1285, fCLK = 120kHz LTC1288, fCLK = 120kHz VCC = 2.7V LTC1285, VCC = 2.7V LTC1288, VCC = 2.7V VCC = 2.7V VCC = 2.7V VCC = 2.7V VCC = 2.7V LTC1285, fCLK = 120kHz LTC1288, fCLK = 120kHz MIN 2.7 2.7 (Note 4) 125.0 141.5 450 2 2 600 3.5 3.5 2 123.0 139.5 TYP MAX 6 6 120 UNITS V V kHz s s ns s s ns s s s s s
2
U
U
U
U
W
WW
U
W
(Notes 1 and 2)
Power Dissipation .............................................. 500mW Operating Temperature Range .................... 0C to 70C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec.)................ 300C
TOP VIEW VREF 1 +IN 2 -IN 3 GND 4 8 7 6 5 VCC CLK DOUT CS/SHDN
ORDER PART NUMBER LTC1285CS8 PART MARKING 1285C ORDER PART NUMBER LTC1288CS8 PART MARKING 1288C
S8 PACKAGE 8-LEAD PLASTIC SO
TJMAX = 150C, JA = 175C/W
TOP VIEW CS/SHDN 1 CH0 2 CH1 3 GND 4 8 7 6 5 VCC (VREF) CLK DOUT DIN
S8 PACKAGE 8-LEAD PLASTIC SO
TJMAX = 150C, JA = 175C/W
U WW
LTC1285/LTC1288
CONVERTER AND MULTIPLEXER CHARACTERISTICS
PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Gain Error Analog Input Range REF Input Range (LTC1285) (Notes 7, 8, and 9) Analog Input Leakage Current (Note 10) (Note 7 and 8) 2.7 VCC 6V
q
DIGITAL AND DC ELECTRICAL CHARACTERISTICS
SYMBOL VIH VIL IIH IIL VOH VOL IOZ ISOURCE ISINK RREF IREF PARAMETER High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Voltage Low Level Output Voltage Hi-Z Output Leakage Output Source Current Output Sink Current Reference Input Resistance (LTC1285) Reference Current (LTC1285) CONDITIONS VCC = 3.6V VCC = 2.7V VIN = VCC VIN = 0V VCC = 2.7V, IO = 10A VCC = 2.7V, IO = 360A VCC = 2.7V, IO = 400A CS = High VOUT = 0V VOUT = VCC CS = VIH CS = VIL CS = VCC tCYC 640s, fCLK 25kHz tCYC = 134s, fCLK = 120kHz CS = VCC LTC1285, tCYC 640s, fCLK 25kHz LTC1285, tCYC = 134s, fCLK = 120kHz LTC1288, tCYC 720s, fCLK 25kHz LTC1288, tCYC = 150s, fCLK = 120kHz
q q q q q q q q q q q q q
ICC
Supply Current
DYNAMIC ACCURACY
SYMBOL S/(N +D) THD SFDR PARAMETER
Signal-to-Noise Plus Distortion Ratio Total Harmonic Distortion (Up to 5th Harmonic) Spurious-Free Dynamic Range Peak Harmonic or Spurious Noise
WU
U
WU
U
(Note 5)
MIN 12 LTC1288 TYP MAX 3/4 1/4 3/4 2 2 3/4 3 8 UNITS Bits LSB LSB LSB LSB V V V 1 A
CONDITIONS
q
MIN 12
q q q q q
LTC1285 TYP MAX 3/4 1/4 3/4 2 2 3/4 3
(Note 6)
8 - 0.05V to VCC + 0.05V 1.5V to VCC + 0.05V 1
(Note 5)
MIN 2 0.8 2.5 - 2.5 2.4 2.1 2.64 2.30 0.4 3 - 10 15 2700 54 0.001 50 50 0.001 150 160 200 210 2.5 70 3.0 320 390 TYP MAX UNITS V V A A V V V A mA mA M k A A A A A A A A
fSMPL = 7.5kHz (LTC1285), fSMPL = 6.6kHz (LTC1288) (Note 5)
CONDITIONS 1kHz Input Signal 1kHz Input Signal 1kHz Input Signal 1kHz Input Signal MIN TYP 67 - 80 88 - 88 MAX UNITS dB dB dB dB
3
LTC1285/LTC1288
AC CHARACTERISTICS
SYMBOL tSMPL PARAMETER Analog Input Sample Time fSMPL (MAX) Maximum Sampling Frequency tCONV tdDO tdis ten thDO tf tr CIN Conversion Time Delay Time, CLK to DOUT Data Valid Delay Time, CS to DOUT Hi-Z Delay Time, CLK to DOUT Enable Time Output Data Remains Valid After CLK DOUT Fall Time DOUT Rise Time Input Capacitance
(Note 5)
CONDITIONS See Operating Sequence LTC1285 LTC1288 See Operating Sequence See Test Circuits See Test Circuits See Test Circuits CLOAD = 100pF See Test Circuits See Test Circuits Analog Inputs, On Channel Analog Inputs, Off Channel Digital Input
q q q q q
MIN q q 7.5 6.6
TYP 1.5
MAX
UNITS CLK Cycles kHz kHz
12 600 220 180 520 60 80 20 5 5 180 180 1500 660 500
CLK Cycles ns ns ns ns ns ns pF pF pF
The q denotes specifications which apply over the full operating temperature range. Note 1: Absolute maximum ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to GND. Note 3: These devices are specified at 3V. For 5V specified devices, see LTC1286 and LTC1298. Note 4: Increased leakage currents at elevated temperatures cause the sample-and-hold to droop, therefore it is recommended that fCLK 75kHz at 70 and fCLK 1kHz at 25C. Note 5: VCC = 2.7V, VREF = 2.5V and CLK = 120kHz unless otherwise specified. Note 6: Linearity error is specified between the actual end points of the A/D transfer curve.
Note 7: Two on-chip diodes are tied to each reference and analog input which will conduct for reference or analog input voltages one diode drop below GND or one diode drop above VCC. This spec allows 50mV forward bias of either diode for 2.7V VCC 6V. This means that as long as the reference or analog input does not exceed the supply voltage by more than 50mV the output code will be correct. To achieve an absolute 0V to 2.7V input voltage range will therefore require a minimum supply voltage of 2.650V over initial tolerance, temperature variations and loading. For 2.7V < VCC 6V, reference and analog input range cannot exceed 6.05V. If reference and analog input range are greater than 6.05V, the output code will not be guaranteed to be correct. Note 8: The supply voltage range for the LTC1285 and the LTC1288 is from 2.7V to 6V. Note 9: Recommended operating conditions Note 10: Channel leakage current is measured after the channel selection.
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs Sample Rate
1000 TA = 25C VCC = 2.7V VREF = 2.5V fCLK = 120kHz 100
SUPPLY CURRENT (A)
SUPPLY CURRENT (A)
LTC1288
SUPPLY CURRENT (A)
10
LTC1285
1 0.1
1 SAMPLE RATE (kHz)
LTC1285/88 * TPC01
4
UW
10
Supply Current vs Temperature
250 LTC1288 fSMPL = 6.6kHz 200 LTC1285 fSMPL = 7.5kHz 150
Shutdown Supply Current vs Clock Rate with CS High and CS Low
9 8 7 6 5 4 3 2 1 0.002 0 1 20 60 80 40 FREQUENCY (kHz) 100 120 CS = VCC CS = 0 (AFTER CONVERSION) TA = 25C VCC = 2.7V VREF = 2.5V
100
50
VCC = 2.7V VREF = 2.5V fCLK = 120kHz 5 25 45 65 85 105 125 TEMPERATURE (C)
LTC1285/88 * TPC02
0 -55 -35 -15
LTC1285/88 * TPC03
LTC1285/LTC1288 TYPICAL PERFORMANCE CHARACTERISTICS
Reference Current vs Sample Rate (LTC1285)
50 45 TA = 25C VCC = 2.7V VREF = 2.5V fCLK = 120kHz
52
REFERENCE CURRENT (A)
CHANGE IN OFFSET (LSB = 1/4096 x VREF)
REFERENCE CURRENT (A)
40 35 30 25 20 15 10 5 0 0
1
2
6 4 3 5 SAMPLE RATE (kHz)
LTC1285/88 * TPC04
Change in Offset vs Temperature
0.20 VCC = 2.7V 0.15 VREF = 2.5V fCLK = 120kHz 0.10 fSMPL = fSMPL(MAX) 0.05 0 - 0.05 - 0.10 - 0.15 - 0.20 0 10 20 40 50 30 TEMPERATURE (C) 60 70
0.50 0.45 CHANGE IN LINEARITY (LSB) 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0
CHANGE IN OFFSET (LSB)
CHANGE IN GAIN (LSB)
LTC1285/88 * TPC07
Differential Nonlinearity vs Code
DIFFERENTIAL NONLINEARITY ERROR (LSB)
1
EFFECTIVE NUMBER OF BITS (ENOBs)
0.5
TA = 25C VCC = 2.7V VREF = 2.5V fCLK = 120kHz
0
- 0.5
-1 0 512 1024 1536 2048 2560 3072 3584 4096 CODE
LTC1285/88 * TPC11
UW
7 8
Reference Current vs Temperature
53 VCC = 2.7V VREF = 2.5V fCLK = 120kHz fSMPL = 7.5kHz 3.0 2.5 2.0 1.5 1.0 0.5 0
Change in Offset vs Reference Voltage
TA = 25C VCC = 2.7V fCLK = 120kHz fSMPL = 7.5kHz
51 50 49 48 47 46 45 44
43 -55 -35 -15
5 25 45 65 85 105 125 TEMPERATURE (C)
LTC1285/88 * TPC05
0.5
1.0
1.5 2.0 2.5 REFERENCE VOLTAGE (V)
3.0
LTC1285/88 * TPC06
Change in Linearity vs Reference Voltage
-10 TA = 25C VCC = 2.7V fCLK = 120kHz fSMPL = 7.5kHz -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 REFERENCE VOLTAGE (V)
LTC1285/88 * TPC08
Change in Gain vs Reference Voltage
TA = 25C VCC = 2.7V fCLK = 120kHz fSMPL = 7.5kHz
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 REFERENCE VOLTAGE (V)
LTC1285/88 * TPC09
Effective Bits and S/(N + D) vs Input Frequency
12 11 10 9 8 7 6 5 4 3 2 1 0 1 10 INPUT FREQUENCY (kHz) 100 TA = 25C VCC = 2.7V fCLK = 120kHz 74 68 62 56 50 S/(N + D) (dB)
LTC1285/88 * TPC12
5
LTC1285/LTC1288 TYPICAL PERFORMANCE CHARACTERISTICS
Spurious-Free Dynamic Range vs Input Frequency
100 90 80 70 60 50 40 30 20 10 0 1 10 INPUT FREQUENCY (kHz) 100 TA = 25C VCC = 2.7V VREF = 2.5V fSMPL = fSMPL(MAX)
SIGNAL-TO-NOISE PLUS DISTORTION (dB)
SPURIOUS-FREE DYNAMIC RANGE (dB)
50 40 30 20 10 0 - 45 - 40 - 35 - 30 - 25 - 20 - 15 - 10 - 5 INPUT LEVEL (dB) 0
ATTENUATION (%)
LTC1285/88 * G13
4096 Point FFT Plot
0 - 20 TA = 25C VCC = 2.7V VREF = 2.5V fIN = 3.05kHz fCLK = 120kHz fSMPL = 7.5kHz 0 - 20
MAGNITUDE (dB)
- 40 - 60 - 80 - 100 - 120 0
- 40 - 60 - 80 - 100 - 120 0
FEEDTHROUGH (dB)
MAGNITUDE (dB)
0.5
1.0
1.5 2.0 2.5 3.0 FREQUENCY (kHz)
Maximum Clock Frequency vs Source Resistance
200 180 TA = 25C VCC = 2.7V VREF = 2.5V
S & H ACQUISITION TIME (ns)
CLOCK FREQUENCY (kHz)
140 120 100 80
VIN +INPUT -INPUT RSOURCE-
CLOCK FREQUENCY (kHz)
160
60 40 20 0 0.1
1 SOURCE RESISTANCE (k)
LTC1285/88 * G19
6
UW
3.5
LTC1285/88 * TPC16
S/(N + D) vs Input Level
TA = 25C 70 VCC = 2.7V VREF = 2.5V 60 fIN = 1kHz fSMPL = fSMPL(MAX) 80
0 10 20 30 40 50 60 70 80 90 100
Attenuation vs Input Frequency
TA = 25C VCC = 2.7V VREF = 2.5V fSMPL = fSMPL(MAX) 1k 10k 100k 1M INPUT FREQUENCY (Hz) 10M
LTC1285/88 * TPC14
LTC1285/86 * TPC15
Intermodulation Distortion
0 TA = 25C VCC = 2.7V VREF = 2.5V f1 = 2.05kHz f2 = 3.05kHz fSMPL = 7.5kHz - 10 - 20 - 30 - 40 - 50 - 60 - 70 - 80 - 90 -100 0.5 1.0 1.5 2.0 2.5 3.0 FREQUENCY (kHz) 3.5 4.0 4.0
Power Supply Feedthrough vs Ripple Frequency
TA = 25C VCC = 2.7V (VRIPPLE = 1mV) VREF = 2.5V fCLK = 120kHZ
1k
10k 100k 1M RIPPLE FREQUENCY (Hz)
10M
LTC1285/88 * TPC17
LTC1285/86 * TPC18
Sample-and-Hold Acquisition Time vs Source Resistance
10000 TA = 25C VCC = 2.7V VREF = 2.5V
Maximum Clock Frequency vs Supply Voltage
300 280 260 240 220 200 180 160 140 TA = 25C VREF = 2.5V
1000
RSOURCE+ VIN +INPUT -INPUT
120 100
10000
10
100 1
10 100 1000 SOURCE RESISTANCE ()
2.5
3.0
3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V)
5.5
6.0
LTC1285/88 * TPC20
LTC1285/88 * TPC21
LTC1285/LTC1288 TYPICAL PERFORMANCE CHARACTERISTICS
Minimum Clock Frequency for 0.1 LSB Error vs Temperature
DIGITAL INPUT LOGIC THRESHOLD VOLTAGE (V)
120 100
VCC = 2.7V VREF = 2.5V
CLOCK FREQUENCY (kHz)
80 60 40 20 2 0
2.0 1.5 1.0 0.5 0 2.5
LEAKAGE CURRENT (nA)
0
10
20
50 40 TEMPERATURE (C)
30
LTC1285/88 * TPC22
PIN FUNCTIONS
LTC1285
VREF (Pin 1): Reference Input. The reference input defines the span of the A/D converter. IN + (Pin 2): Positive Analog Input. IN - (Pin 3): Negative Analog Input. GND (Pin 4): Analog Ground. GND should be tied directly to an analog ground plane. CS/SHDN (Pin 5): Chip Select Input. A logic low on this input enables the LTC1285. A logic high on this input disables and powers down the LTC1285. DOUT (Pin 6): Digital Data Output. The A/D conversion result is shifted out of this output. CLK (Pin 7): Shift Clock. This clock synchronizes the serial data transfer and determines conversion speed. VCC (Pin 8): Power Supply Voltage. This pin provides power to the A/D converter. It must be kept free of noise and ripple by bypassing directly to the analog ground plane.
UW
60 70
Digital Input Logic Threshold vs Supply Voltage
3.0 TA = 25C 2.5
100 1000
Input Channel Leakage Current vs Temperature
VCC = 2.7V VREF = 2.5V
10
1 ON CHANNEL OFF CHANNEL 0.1
3.0
5.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V)
5.5
6.0
0.01 -55 -35 -15
5 25 45 65 85 105 125 TEMPERATURE (C)
LTC1285/88 * TPC24
LTC1285/88 * TPC23
U
U
U
LTC1288
CS/SHDN (Pin 1): Chip Select Input. A logic low on this input enables the LTC1288. A logic high on this input disables and powers down the LTC1288. CH0 (Pin 2): Analog Input. CH1 (Pin 3): Analog Input. GND (Pin 4): Analog Ground. GND should be tied directly to an analog ground plane. DIN (Pin 5): Digital Data Input. The multiplexer address is shifted into this input. DOUT (Pin 6): Digital Data Output. The A/D conversion result is shifted out of this output. CLK (Pin 7): Shift Clock. This clock synchronizes the serial data transfer and determines conversion speed. VCC /VREF (Pin 8): Power Supply and Reference Voltage. This pin provides power and defines the span of the A/D converter. It must be kept free of noise and ripple by bypassing directly to the analog ground plane.
7
LTC1285/LTC1288
BLOCK DIAGRAM
IN + (CH0)
IN - (CH1)
GND PIN NAMES IN PARENTHESES REFER TO THE LTC1288
TEST CIRCUITS
Load Circuit for tdDO, tr and tf
1.4V
3k DOUT 100pF
LTC1285/88 * TC01
TEST POINT
Voltage Waveforms for DOUT Delay Times, tdDO
CLK
VIL tdDO
3k DOUT VCC tdis WAVEFORM 2, ten tdis WAVEFORM 1
LTC1285/88 * TC04
DOUT
VOH VOL
LTC1285/88 * TC03
8
+
-
W
CS/SHDN VCC (VCC/ V REF) (DIN) CLK BIAS AND SHUTDOWN CIRCUIT CSAMPLE SERIAL PORT DOUT SAR MICROPOWER COMPARATOR CAPACITIVE DAC
LTC1285/88 * BD
VREF
Voltage Waveforms for DOUT Rise and Fall Times, tr, tf
DOUT VOH VOL tr tf
LTC1285/88 * TC02
Load Circuit for tdis and ten
TEST POINT
100pF
LTC1285/LTC1288
TEST CIRCUITS
Voltage Waveforms for tdis
LTC1285
Voltage Waveforms for ten
VIH
CS
CS
DOUT WAVEFORM 1 (SEE NOTE 1) tdis DOUT WAVEFORM 2 (SEE NOTE 2)
90%
CLK 1 2
10%
DOUT ten VOL
B11
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL. NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL.
LTC1285/88 * TC05
LTC1285/88 * TC06
Voltage Waveforms for ten
LTC1288 CS
DIN
START
CLK
1
2
3
4
DOUT ten
B11 VOL
LTC1285/88 * TC07
9
LTC1285/LTC1288
APPLICATION INFORMATION
OVERVIEW The LTC1285 and LTC1288 are 3V micropower, 12-bit, successive approximation sampling A/D converters. The LTC1285 typically draws 160A of supply current when sampling at 7.5kHz while the LTC1288 nominally consumes 210A of supply current when sampling at 6.6 kHz. The extra 50A of supply current on the LTC1288 comes from the reference input which is intentionally tied to the supply. Supply current drops linearly as the sample rate is reduced (see Supply Current vs Sample Rate). The ADCs automatically power down when not performing conversions, drawing only leakage current. They are packaged in 8-pin SO and DIP packages. The LTC1285 and LTC1288 operate on a single supply from 2.7V to 6V. Both the LTC1285 and the LTC1288 contain a 12-bit, switched-capacitor ADC, a sample-and-hold, and a serial port (see Block Diagram). Although they share the same
tCYC CS tsuCS CLK POWER DOWN
DOUT
HI-Z tSMPL
NULL BIT B11 B10 B9 (MSB)
B8
B7
B6
B5
B4
tCONV
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT LSB-FIRST DATA THEN FOLLOWED WITH ZEROS INDEFINITELY. tCYC CS
tsuCS CLK
DOUT
HI-Z
NULL BIT
B11 B10 (MSB)
B9
B8
B7 tCONV
B6
B5
B4
tSMPL
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY. tDATA: DURING THIS TIME, THE BIAS CIRCUIT AND THE COMPARATOR POWER DOWN AND THE REFERENCE INPUT BECOMES A HIGH IMPEDANCE NODE, LEAVING THE CLK RUNNING TO CLOCK OUT LSB-FIRST DATA OR ZEROES.
LTC1285/88 * F01
Figure 1. LTC1285 Operating Sequence
10
U
W
UU
basic design, the LTC1285 and LTC1288 differ in some respects. The LTC1285 has a differential input and has an external reference input pin. It can measure signals floating on a DC common-mode voltage and can operate with reduced spans to 1.5V. Reducing the spans allows it to achieve 366V resolution. The LTC1288 has a two-channel input multiplexer and can convert either channel with respect to ground or the difference between the two. The reference input is tied to the supply pin. SERIAL INTERFACE The 2-channel LTC1288 communicates with microprocessors and other external circuitry via a synchronous, half duplex, 4-wire serial interface. The single channel LTC1285 uses a 3-wire interface (see Operating Sequence in Figures 1 and 2).
B3
B2
B1
B0*
HI-Z
NULL BIT B11 B10
B9
B8
tDATA
POWER DOWN
B3
B2
B1
B0
B1
B2
B3
B4
B5
B6
B7 B8
B9 B10 B11*
HI-Z
tDATA
LTC1285/LTC1288
APPLICATION INFORMATION
MSB-First Data (MSBF = 0)
tCYC CS tsuCS CLK POWER DOWN
START DIN SGL/ DIFF DOUT
ODD/ SIGN DON'T CARE MSBF NULL HI-Z BIT tSMPL
B11 B10 B9 (MSB)
B8
B7
B6 tCONV
B5
MSB-First Data (MSBF = 1)
tCYC CS tsuCS CLK START DIN SGL/ DIFF DOUT HI-Z tSMPL MSBF NULL BIT B11 B10 B9 (MSB) HI-Z tDATA ODD/ SIGN DON'T CARE
B8
B7
B6
B5
tCONV
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY. tDATA: DURING THIS TIME, THE BIAS CIRCUIT AND THE COMPARATOR POWER DOWN AND THE REFERENCE INPUT BECOMES A HIGH IMPEDANCE NODE, LEAVING THE CLK RUNNING TO CLOCK OUT LSB-FIRST DATA OR ZEROES.
LTC1285/88 * F02
Figure 2. LTC1288 Operating Sequence Example: Differential Inputs (CH+, CH-)
U
W
UU
B4
B3
B2
B1
B0
B1
B2
B3
B4
B5
B6 tDATA
B7
B8
B9 B10 B11*
HI-Z
POWER DOWN
B4
B3
B2
B1 B0*
11
LTC1285/LTC1288
APPLICATION INFORMATION
Data Transfer The CLK synchronizes the data transfer with each bit being transmitted on the falling CLK edge and captured on the rising CLK edge in both transmitting and receiving systems. The LTC1285 does not require a configuration input word and has no DIN pin. A falling CS initiates data transfer as shown in the LTC1285 operating sequence. After CS falls the second CLK pulse enables DOUT. After one null bit the A/D conversion result is output on the DOUT line. Bringing CS high resets the LTC1285 for the next data exchange. The LTC1288 first receives input data and then transmits back the A/D conversion result (half duplex). Because of the half duplex operation, DIN and DOUT may be tied together allowing transmission over just 3 wires: CS, CLK and DATA (DIN/DOUT). Data transfer is initiated by a falling chip select (CS) signal. After CS falls the LTC1288 looks for a start bit. After the start bit is received, the 3-bit input word is shifted into the DIN input which configures the LTC1288 and starts the conversion. After one null bit, the result of the conversion is output on the DOUT line. At the end of the data exchange CS should be brought high. This resets the LTC1288 in preparation for the next data exchange.
CS DIN 1 DOUT 1 SHIFT MUX ADDRESS IN 1 NULL BIT SHIFT A/D CONVERSION RESULT OUT
LTC1285/88 * AI01
DIN 2 DOUT 2
SINGLE-ENDED MUX MODE DIFFERENTIAL MUX MODE
Input Data Word The LTC1285 requires no DIN word. It is permanently configured to have a single differential input. The conversion result appears on the DOUT line. The data format is MSB first followed by the LSB sequence. This provides easy interface to MSB or LSB first serial ports. For MSB first data the CS signal can be taken high after B0 (see Figure 1). The LTC1288 clocks data into the DIN input on
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the rising edge of the clock. The input data words are defined as follows:
START SGL/ DIFF ODD/ SIGN MSBF
MUX MSB FIRST/ ADDRESS LSB FIRST
LTC1285/88 * AI02
Start Bit The first "logical one" clocked into the DIN input after CS goes low is the start bit. The start bit initiates the data transfer. The LTC1288 will ignore all leading zeros which precede this logical one. After the start bit is received, the remaining bits of the input word will be clocked in. Further inputs on the DIN pin are then ignored until the next CS cycle. Multiplexer (MUX) Address The bits of the input word following the START bit assign the MUX configuration for the requested conversion. For a given channel selection, the converter will measure the voltage between the two channels indicated by the "+" and "-" signs in the selected row of the following tables. In single-ended mode, all input channels are measured with respect to GND.
LTC1288 Channel Selection
MUX ADDRESS SGL/DIFF ODD/SIGN 1 0 1 1 0 0 0 1 CHANNEL # 0 1 + + + - - + GND - -
LTC1285/88 * AI03
MSB First/LSB First (MSBF) The output data of the LTC1288 is programmed for MSB first or LSB first sequence using the MSBF bit. When the MSBF bit is a logical one, data will appear on the DOUT line in MSB first format. Logical zeros will be filled in indefinitely following the last data bit. When the MSBF bit is a logical zero, LSB first data will follow the normal MSB first data on the DOUT line (see Operating Sequence).
LTC1285/LTC1288
APPLICATION INFORMATION
Transfer Curve The LTC1285/LTC1288 are permanently configured for unipolar only. The input span and code assignment for this conversion type are shown in the following figures.
Transfer Curve
111111111111 111111111110
* * *
000000000001 000000000000 VIN
1LSB =
VREF 4096
Output Code
1000
OUTPUT CODE 11111111111111 11111111111110 * * * 00000000000001 00000000000000 INPUT VOLTAGE VREF - 1LSB VREF - 2LSB * * * 1LSB 0V INPUT VOLTAGE (VREF = 5.000V)
SUPPLY CURRENT (A)
4.99878V 4.99756V * * * 0.00122V 0V
LTC1285/88 * AI05
Operation with DIN and DOUT Tied Together The LTC1288 can be operated with DIN and DOUT tied together. This eliminates one of the lines required to communicate to the microprocessor (MPU). Data is transmitted in both directions on a single wire. The processor pin connected to this data line should be configurable as
CS
1 0.1 1 10 SAMPLE FREQUENCY (kHz) 100
1 CLK
2
DATA (DIN/DOUT)
START
SGL/DIFF
MPU CONTROLS DATA LINE AND SENDS MUX ADDRESS TO LTC1288 PROCESSOR MUST RELEASE DATA LINE AFTER 4TH RISING CLK AND BEFORE THE 4TH FALLING CLK
Figure 3. LTC1288 Operation with DIN and DOUT Tied Together
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either an input or an output. The LTC1288 will take control of the data line and drive it low on the 4th falling CLK edge after the start bit is received (see Figure 3). Therefore the processor port line must be switched to an input before this happens to avoid a conflict. In the Typical Applications section, there is an example of interfacing the LTC1288 with DIN and DOUT tied together to the Intel 8051 MPU. ACHIEVING MICROPOWER PERFORMANCE With typical operating currents of 160A and automatic shutdown between conversions, the LTC1285/LTC1288 achieves extremely low power consumption over a wide range of sample rates (see Figure 4). The auto-shutdown allows the supply curve to drop with reduced sample rate.
TA = 25C VCC = 2.7V VREF = 2.5V fCLK = 120kHz 100
0V
1LSB
VREF
VREF-1LSB
VREF-2LSB
LTC1285/88 * AI04
10
LTC1285/88 * F04
Figure 4. Automatic Power Shutdown Between Conversions Allows Power Consumption to Drop with Sample Rate
MSBF BIT LATCHED BY LTC1288
3
4
ODD/SIGN
MSBF
B11
B10
***
LTC1288 CONTROLS DATA LINE AND SENDS A/D RESULT BACK TO MPU LTC1288 TAKES CONTROL OF DATA LINE ON 4TH FALLING CLK
LTC1285/88 F03
13
LTC1285/LTC1288
APPLICATION INFORMATION
Several things must be taken into account to achieve such a low power consumption. Shutdown The LTC1285/LTC1288 are equipped with automatic shutdown features. They draw power when the CS pin is low and shut down completely when that pin is high. The bias circuit and comparator powers down and the reference input becomes high impedance at the end of each conversion leaving the CLK running to clock out the LSB first data or zeroes (see Figures 1 and 2). If the CS is not running railto-rail, the input logic buffer will draw current. This current may be large compared to the typical supply current. To obtain the lowest supply current, bring the CS pin to ground when it is low and to supply voltage when it is high. When the CS pin is high (= supply voltage), the converter is in shutdown mode and draws only leakage current. The status of the DIN and CLK input have no effect on supply current during this time. There is no need to stop DIN and CLK with CS = high; they can continue to run without drawing current. Minimize CS Low Time In systems that have significant time between conversions, lowest power drain will occur with the minimum CS low time. Bringing CS low, transferring data as quickly as possible, and then bringing it back high will result in the
9 8 7
SUPPLY CURRENT (A)
TA = 25C VCC = 2.7V VREF = 2.5V
6 5 4 3 2 1 CS = 0 (AFTER CONVERSION)
0.002 0 1 20
CS = VCC 60 80 40 FREQUENCY (kHz) 100 120
LTC1285/88 * TPC03
Figure 5. Shutdown Current with CS High is 1nA Typically, Regardless of the Clock. Shutdown Current with CS = Ground Varies From 1A at 1kHz to 9A at 120kHz
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lowest current drain. This minimizes the amount of time the device draws power. After a conversion the ADC automatically shuts down even if CS is held low (see Figures 1 and 2). If the clock is left running to clock out LSB-data or zero, the logic will draw a small current. Figure 5 shows that the typical supply current with CS = ground varies from 1A at 1kHz to 9A at 120kHz. When CS = VCC, the logic is gated off and no supply current is drawn regardless of the clock frequency. DOUT Loading Capacitive loading on the digital output can increase power consumption. A 100pF capacitor on the DOUT pin can add more than 16.2A to the supply current at a 120kHz clock frequency. An extra 16.2A or so of current goes into charging and discharging the load capacitor. The same goes for digital lines driven at a high frequency by any logic. The C x V x f currents must be evaluated and the troublesome ones minimized. OPERATING ON OTHER THAN 3V SUPPLIES Both the LTC1285 and the LTC1288 operate from a 2.7V to 6V supply. To operate the LTC1285/LTC1288 on other than 3V supplies a few things must be kept in mind. Input Logic Levels The input logic levels of CS, CLK and DIN are made to meet TTL on a 3V supply. When the supply voltage varies, the input logic levels also change. For the LTC1285/ LTC1288 to sample and convert correctly, the digital inputs have to be in the proper logical low and high levels relative to the operating supply voltage (see typical curve of Digital Input Logic Threshold vs Supply Voltage). If achieving micropower consumption is desirable, the digital inputs must go rail-to-rail between supply voltage and ground (see ACHIEVING MICROPOWER PERFORMANCE section). Clock Frequency The maximum recommended clock frequency is 120kHz for the LTC1285/LTC1288 running off a 3V supply. With the supply voltage changing, the maximum clock frequency for the devices also changes (see the typical curve
LTC1285/LTC1288
APPLICATION INFORMATION
of Maximum Clock Rate vs Supply Voltage). If the maximum clock frequency is used, care must be taken to ensure that the device converts correctly. Mixed Supplies It is possible to have a microprocessor running off a 5V supply and communicate with the LTC1285/LTC1288 operating on a 3V supply. The inputs of CS, CLK and DIN of the LTC1285/LTC1288 have no problem to take a voltage swing from 0V to 5V. With the LTC1285 operating on a 3V supply, the output of DOUT may only go between 0V and 3V. The 3V output level is higher enough to trip a TTL input of the MPU. Figure 6 shows a 3V powered LTC1285 interfacing a 5V system.
3V 4.7F
MPU (e.g. 8051) 3V DIFFERENTIAL INPUTS COMMON-MODE RANGE 0V TO 3V VREF +IN -IN GND LTC1285 VCC CLK DOUT CS P1.4 P1.3 P1.2
Figure 6. Interfacing a 3V Powered LTC1285 to a 5V System
CS
CLK
DIN
START
DOUT 1ST BIT TEST "-" INPUT MUST SETTLE DURING THIS TIME "+" INPUT
"-" INPUT
LTC1285/88 * F07
Figure 7. LTC1288 "+" and "-" Input Settling Windows
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BOARD LAYOUT CONSIDERATIONS Grounding and Bypassing The LTC1285/LTC1288 are easy to use if some care is taken. They should be used with an analog ground plane and single point grounding techniques. The GND pin should be tied directly to the ground plane. The VCC pin should be bypassed to the ground plane with a 10F tantalum capacitor with leads as short as possible. If the power supply is clean, the LTC1285/LTC1288 can also operate with smaller 1F or less surface mount or ceramic bypass capacitors. All analog inputs should be referenced directly to the single point ground. Digital inputs and outputs should be shielded from and/or routed away from the reference and analog circuitry. SAMPLE-AND-HOLD Both the LTC1285 and the LTC1288 provide a built-in sample-and-hold (S&H) function to acquire signals. The S&H of the LTC1285 acquires input signals from "+" input relative to "-" input during the tSMPL time (see Figure 1). However, the S&H of the LTC1288 can sample input signals in the single-ended mode or in the differential inputs during the tSMPL time (see Figure 7).
SAMPLE "+" INPUT MUST SETTLE DURING THIS TIME tSMPL tCONV HOLD
5V
LTC1285/88 * F06
SGL/DIFF
MSBF
DON'T CARE
B11
15
LTC1285/LTC1288
APPLICATION INFORMATION
Single-Ended Inputs The sample-and-hold of the LTC1288 allows conversion of rapidly varying signals. The input voltage is sampled during the tSMPL time as shown in Figure 7. The sampling interval begins as the bit preceding the MSBF bit is shifted in and continues until the falling CLK edge after the MSBF bit is received. On this falling edge, the S&H goes into hold mode and the conversion begins. Differential Inputs With differential inputs, the ADC no longer converts just a single voltage but rather the difference between two voltages. In this case, the voltage on the selected "+" input is still sampled and held and therefore may be rapidly time varying just as in single-ended mode. However, the voltage on the selected "-" input must remain constant and be free of noise and ripple throughout the conversion time. Otherwise, the differencing operation may not be performed accurately. The conversion time is 12 CLK cycles. Therefore, a change in the "-" input voltage during this interval can cause conversion errors. For a sinusoidal voltage on the "-" input this error would be: VERROR (MAX) = VPEAK x 2 x x f("-") x 12/fCLK Where f("-") is the frequency of the "-" input voltage, VPEAK is its peak amplitude and fCLK is the frequency of the CLK. In most cases VERROR will not be significant. For a 60Hz signal on the "-" input to generate a 1/4LSB error (152V) with the converter running at CLK = 120kHz, its peak value would have to be 4.03mV. ANALOG INPUTS Because of the capacitive redistribution A/D conversion techniques used, the analog inputs of the LTC1285/ LTC1288 have capacitive switching input current spikes. These current spikes settle quickly and do not cause a problem. However, if large source resistances are used or if slow settling op amps drive the inputs, care must be taken to insure that the transients caused by the current spikes settle completely before the conversion begins. "+" Input Settling The input capacitor of the LTC1285 is switched onto "+" input during the tSMPL time (see Figure 1) and samples the input signal within that time. However, the input capacitor of the LTC1288 is switched onto "+" input during the sample phase (tSMPL, see Figure 7). The sample phase is 1 1/2 CLK cycles before conversion starts. The voltage on the "+" input must settle completely within tSMPLE for the LTC1285 and the LTC1288 respectively. Minimizing RSOURCE+ and C1 will improve the input settling time. If a large "+" input source resistance must be used, the sample time can be increased by using a slower CLK frequency. "-" Input Settling At the end of the tSMPL, the input capacitor switches to the "-" input and conversion starts (see Figures 1 and 7). During the conversion, the "+" input voltage is effectively "held" by the sample-and-hold and will not affect the conversion result. However, it is critical that the "-" input voltage settles completely during the first CLK cycle of the conversion time and be free of noise. Minimizing RSOURCE- and C2 will improve settling time. If a large "-" input source resistance must be used, the time allowed for settling can be extended by using a slower CLK frequency. Input Op Amps When driving the analog inputs with an op amp it is important that the op amp settle within the allowed time (see Figure 7). Again, the"+" and "-" input sampling times can be extended as described above to accommodate slower op amps. Most op amps, including the LT1006 and LT1413 single supply op amps, can be made to settle well even with the minimum settling windows of 12.5s ("+" input) which occur at the maximum clock rate of 120kHz. Source Resistance The analog inputs of the LTC1285/LTC1288 look like a 20pF capacitor (CIN) in series with a 500 resistor (RON) as shown in Figure 8. CIN gets switched between the
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LTC1285/LTC1288
APPLICATION INFORMATION
selected "+" and "-" inputs once during each conversion cycle. Large external source resistors and capacitances will slow the settling of the inputs. It is important that the overall RC time constants be short enough to allow the analog inputs to completely settle within the allowed time.
RSOURCE + VIN + C1 RSOURCE - VIN - C2
LTC1285/88 * F08
"+" INPUT LTC1285 LTC1288 RON = 500 CIN = 20pF
"-" INPUT
Figure 8. Analog Input Equivalent Circuit
RC Input Filtering It is possible to filter the inputs with an RC network as shown in Figure 9. For large values of CF (e.g., 1F), the capacitive input switching currents are averaged into a net DC current. Therefore, a filter should be chosen with a small resistor and large capacitor to prevent DC drops across the resistor. The magnitude of the DC current is approximately IDC = 20pF x VIN /tCYC and is roughly proportional to VIN. When running at the minimum cycle time of 133.3s, the input current equals 0.375A at VIN = 2.5V. In this case, a filter resistor of 160 will cause 0.1LSB of full-scale error. If a larger filter resistor must be used, errors can be eliminated by increasing the cycle time.
RFILTER VIN CFILTER IDC "+" LTC1285 "-"
LTC1285/88 * F09
Figure 9. RC Input Filtering
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Input Leakage Current Input leakage currents can also create errors if the source resistance gets too large. For instance, the maximum input leakage specification of 1A (at 125C) flowing through a source resistance of 240 will cause a voltage drop of 240V or 0.4LSB. This error will be much reduced at lower temperatures because leakage drops rapidly (see typical curve of Input Channel Leakage Current vs Temperature). REFERENCE INPUTS The reference input of the LTC1285 is effectively a 50k resistor from the time CS goes low to the end of the conversion. The reference input becomes a high impedence node at any other time (see Figure 10). Since the voltage on the reference input defines the voltage span of the A/D converter, the reference input should be driven by a reference with low ROUT (ex. LT1004, LT1019 and LT1021) or a voltage source with low ROUT.
REF+ 1 ROUT VREF GND 4
LTC1285/88 * F10
LTC1285
Figure 10. Reference Input Equivalent Circuit
Reduced Reference Operation The minimum reference voltage of the LTC1288 is limited to 2.7V because the VCC supply and reference are internally tied together. However, the LTC1285 can operate with reference voltages below 1.5V. The effective resolution of the LTC1285 can be increased by reducing the input span of the converter. The LTC1285 exhibits good linearity and gain over a wide range of reference voltages (see typical curves of Change in Linearity vs Reference Voltage and Change in Gain vs Reference
17
LTC1285/LTC1288
APPLICATION INFORMATION
Voltage). However, care must be taken when operating at low values of VREF because of the reduced LSB step size and the resulting higher accuracy requirement placed on the converter. The following factors must be considered when operating at low VREF values: 1. Offset 2. Noise 3. Conversion speed (CLK frequency) Offset with Reduced VREF The offset of the LTC1285 has a larger effect on the output code. When the ADC is operated with reduced reference voltage. The offset (which is typically a fixed voltage) becomes a larger fraction of an LSB as the size of the LSB is reduced. The typical curve of Change in Offset vs Reference Voltage shows how offset in LSBs is related to reference voltage for a typical value of VOS. For example, a VOS of 122V which is 0.2LSB with a 2.5V reference becomes 1LSB with a 1V reference and 5LSBs with a 0.2V reference. If this offset is unacceptable, it can be corrected digitally by the receiving system or by offsetting the "-" input of the LTC1285. Noise with Reduced VREF The total input referred noise of the LTC1285 can be reduced to approximately 400V peak-to-peak using a ground plane, good bypassing, good layout techniques and minimizing noise on the reference inputs. This noise is insignificant with a 2.5V reference but will become a larger fraction of an LSB as the size of the LSB is reduced. For operation with a 2.5V reference, the 400V noise is only 0.66LSB peak-to-peak. In this case, the LTC1285 noise will contribute a little bit of uncertainty to the output code. However, for reduced references the noise may become a significant fraction of an LSB and cause undesirable jitter in the output code. For example, with a 1.25V reference this same 400V noise is 1.32LSB peak-to-peak. This will reduce the range of input voltages over which a stable output code can be achieved by 1LSB. If the reference is further reduced to 1V, the 400V noise becomes equal to 3.3LSBs and a stable code may be difficult to achieve. In this case averaging multiple readings may be necessary. This noise data was taken in a very clean setup. Any setup induced noise (noise or ripple on VCC, VREF or VIN) will add to the internal noise. The lower the reference voltage to be used the more critical it becomes to have a clean, noise free setup. Conversion Speed with Reduced VREF With reduced reference voltages, the LSB step size is reduced and the LTC1285 internal comparator overdrive is reduced. Therefore, it may be necessary to reduce the maximum CLK frequency when low values of VREF are used. DYNAMIC PERFORMANCE The LTC1285/LTC1288 have exceptional sampling capability. Fast Fourier Transform (FFT) test techniques are used to characterize the ADC's frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC's spectral content can be examined for frequencies outside the fundamental. Figure 11 shows a typical LTC1285 plot.
0 - 20 TA = 25C VCC = 2.7V VREF = 2.5V fIN = 3.05kHz fCLK = 120kHz fSMPL = 7.5kHz
MAGNITUDE (dB)
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- 40 - 60 - 80 - 100 - 120 0
0.5
1.0
1.5 2.0 2.5 3.0 FREQUENCY (kHz)
3.5
4.0
LTC1285/88 * TPC16
Figure 11. LTC1285 Non-Averaged, 4096 Point FFT Plot
LTC1285/LTC1288
APPLICATION INFORMATION
Signal-to-Noise Ratio The Signal-to-Noise plus Distortion Ratio (S/N + D) is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the ADC's output. The output is band limited to frequencies above DC and below one half the sampling frequency. Figure 12 shows a typical spectral content with a 7.5kHz sampling rate.
12
EFFECTIVE NUMBER OF BITS (ENOBs)
74 68 62 56 50
11 10 9 8 7 6 5 4 3 2 1 0 1 10 INPUT FREQUENCY (kHz) TA = 25C VCC = 2.7V fCLK = 120kHz
100
LTC1285/88 * TPC12
Figure 12. Effective Bits and S/(N + D) vs Input Frequency
Effective Number of Bits The Effective Number of Bits (ENOBs) is a measurement of the resolution of an ADC and is directly related to S/(N+D) by the equation: ENOB = [S/(N + D) - 1.76]/6.02 where S/(N + D) is expressed in dB. At the maximum sampling rate of 7.5kHz with a 2.7V supply, the LTC1285 maintains above 10.7 ENOBs at 10kHz input frequency. Above 10kHz the ENOBs gradually decline, as shown in Figure 12, due to increasing second harmonic distortion. The noise floor remains low. Total Harmonic Distortion Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half of the sampling frequency. THD is defined as:
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THD = 20log
2 2 2 2 V2 + V3 + V4 + ... + VN
V1
where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through the Nth harmonics. The typical THD specification in the Dynamic Accuracy table includes the 2nd through 5th harmonics. With a 1kHz input signal, the LTC1285/LTC1288 have typical THD of 80dB with VCC = 2.7V. Intermodulation Distortion
S/(N + D) (dB)
If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency.
If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. For example, the 2nd order IMD terms include (fa + fb) and (fa - fb) while 3rd order IMD terms include (2fa + fb), (2fa - fb), (fa + 2fb), and (fa - 2fb). If the two input sine waves are equal in magnitudes, the value (in dB) of the 2nd order IMD products can be expressed by the following formula:
amplitude fa fb IMD fa fb = 20log amplitude at fa
(
)
(
)

For input frequencies of 2.05kHz and 3.05kHz, the IMD of the LTC1285/LTC1288 is 72dB with a 2.7V supply. Peak Harmonic or Spurious Noise The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This value is expressed in dBs relative to the RMS value of a fullscale input signal.
19
LTC1285/LTC1288
TYPICAL APPLICATIONS N
MICROPROCESSOR INTERFACES The LTC1285/LTC1288 can interface directly without external hardware to most popular microprocessor (MPU) synchronous serial formats (see Table 1). If an MPU without a dedicated serial port is used, then 3 or 4 of the MPU's parallel port lines can be programmed to form the serial link to the LTC1285/LTC1288. Included here is one serial interface example and one example showing a parallel port programmed to form the serial interface. Motorola SPI (MC68HC11) The MC68HC11 has been chosen as an example of an MPU with a dedicated serial port. This MPU transfers data MSB -first and in 8-bit increments. The DIN word sent to the data register starts with the SPI process. With three 8-bit transfers, the A/D result is read into the MPU. The second 8-bit transfer clocks B11 through B8 of the A/D conversion result into the processor. The third 8-bit transfer clocks the remaining bits, B7 through B0, into the MPU. The data is right justified into two memory locations. ANDing the second byte with OFHEX clears the four most significant bits. This operation was not included in the code. It can be inserted in the data gathering loop or outside the loop when the data is processed. MC68HC11 Code In this example the DIN word configures the input MUX for a single-ended input to be applied to CHO. The conversion result is output MSB-first.
Table 1. Microprocessor with Hardware Serial Interfaces Compatible with the LTC1286/LTC1298
PART NUMBER Motorola MC6805S2,S3 MC68HC11 MC68HC05 RCA CDP68HC05 Hitachi HD6305 HD63705 HD6301 HD63701 HD6303 HD64180 National Semiconductor COP400 Family COP800 Family NS8050U HPC16000 Family Texas Instruments TMS7002 TMS7042 TMS70C02 TMS70C42 TMS32011* TMS32020 Intel 8051 Bit Manipulation on Parallel Port * Requires external hardware MICROWIRE and MICROWIRE/PLUS are trademarks of National Semiconductor Corp. Serial Port Serial Port Serial Port Serial Port Serial Port Serial Port MICROWIRE MICROWIRE/PLUS MICROWIRE/PLUS MICROWIRE/PLUS SCI Synchronous SCI Synchronous SCI Synchronous SCI Synchronous SCI Synchronous CSI/O SPI SPI SPI SPI TYPE OF INTERFACE
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TYPICAL APPLICATIONS N
Timing Diagram for Interface to the MC68HC11
CS
CLK
DIN
DOUT
MPU TRANSMIT WORD
0
0
0
0
0
0
0
BYTE 1 MPU RECEIVED WORD
?
?
?
?
?
?
?
BYTE 1
DOUT FROM LTC1298 STORED IN MC68HC11 RAM MSB #62 0 0 0 0 B11 B10 B9 B8 BYTE 1 ANALOG INPUTS B3 B2 B1 B0 BYTE 2 CH1 CH0 CS CLK LTC1288 DOUT DIN D0 SCK MC68HC11 MISO MOSI
LTC1285/88 * TA04
LSB #63 B7 B6 B5 B4
LABEL MNEMONIC LDAA STAA LDAA STAA LDAA STAA LDAA STAA LDAA STAA LDX LOOP BCLR LDAA STAA LDAA
OPERAND #$50 $1028 #$1B $1009 #$01 $50 #$A0 $51 #$00 $52 #$1000 $08,X,#$01 $50 $102A $1029
COMMENTS CONFIGURATION DATA FOR SPCR LOAD DATA INTO SPCR ($1028) CONFIG. DATA FOR PORT D DDR LOAD DATA INTO PORT D DDR LOAD DIN WORD INTO ACC A LOAD DIN DATA INTO $50 LOAD DIN WORD INTO ACC A LOAD DIN DATA INTO $51 LOAD DUMMY DIN WORD INTO ACC A LOAD DUMMY DIN DATA INTO $52 LOAD INDEX REGISTER X WITH $1000 D0 GOES LOW (CS GOES LOW) LOAD DIN INTO ACC A FROM $50 LOAD DIN INTO SPI, START SCK CHECK SPI STATUS REG
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START
SGL/ DIFF
ODD/ SIGN MSBF
DON'T CARE
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
1
SGL/ DIFF
ODD/ SIGN MSBF
X BYTE 2
X
X
X
X
X
X
X
X
X
X
X
X
BYTE 3 (DUMMY)
?
?
?
?
0
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
LTC1285/88 * TA03
BYTE 2
BYTE 3
Hardware and Software Interface to the MC68HC11
LABEL MNEMONIC WAIT1 BPL LDAA STAA WAIT2 LDAA BPL LDAA STAA LDAA STAA WAIT3 LDAA BPL BSET LDAA STAA JMP
OPERAND WAIT1 $51 $102A $1029 WAIT2 $102A $62 $52 $102A $1029 WAIT3 $08,X#$01 $102A $63 LOOP
COMMENTS CHECK IF TRANSFER IS DONE LOAD DIN INTO ACC A FROM $51 LOAD DIN INTO SPI, START SCK CHECK SPI STATUS REG CHECK IF TRANSFER IS DONE LOAD LTC1288 MSBs INTO ACC A STORE MSBs IN $62 LOAD DUMMY INTO ACC A FROM $52 LOAD DUMMY DIN INTO SPI, START SCK CHECK SPI STATUS REG CHECK IF TRANSFER IS DONE DO GOES HIGH (CS GOES HIGH) LOAD LTC1288 LSBs IN ACC STORE LSBs IN $63 START NEXT CONVERSION
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LTC1285/LTC1288
TYPICAL APPLICATIONS N
Interfacing to the Parallel Port of the INTEL 8051 Family The Intel 8051 has been chosen to demonstrate the interface between the LTC1288 and parallel port microprocessors. Normally the CS, CLK and DIN signals would be generated on 3 port lines and the DOUT signal read on a 4th port line. This works very well. However, we will demonstrate here an interface with the DIN and DOUT of the LTC1288 tied together as described in the SERIAL INTERFACE section. This saves one wire. The 8051 first sends the start bit and MUX address to the LTC1288 over the data line connected to P1.2. Then P1.2 is reconfigured as an input (by writing to it a one) and the 8051 reads back the 12-bit A/D result over the same data line.
CS CLK LTC1288 DOUT DIN P1.4 P1.3 P1.2 MUX ADDRESS A/D RESULT
LTC1285/88 * TA01
ANALOG INPUTS
DOUT FROM 1288 STORED IN 8501 RAM
MSB R2 B11 B10 B9 B8 B7 B6 B5 B4 LSB R3 B3 B2 B1 B0 0 0 0 0
CS
CLK
DATA (DIN/DOUT)
START
SGL/ DIFF ODD/ MSBF SIGN
8051 P1.2 OUTPUTS DATA TO LTC1288 8051 P1.2 RECONFIGURED AS IN INPUT AFTER THE 4TH RISING CLK AND BEFORE THE 4TH FALLING CLK
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LABEL
MNEMONIC MOV SETB CLR MOV RLC CLR MOV SETB DJNZ MOV CLR MOV MOV RLC SETB CLR DJNZ MOV CLR MOV MOV RLC SETB CLR DJNZ MOV RRC DJNZ MOV SETB
OPERAND A, #FFH P1.4 P1.4 R4, #04 A P1.3 P1.2, C P1.3 R4, LOOP 1 P1, #04 P1.3 R4, #09 C, P1.2 A P1.3 P1.3 R4, LOOP 2 R2, A A R4, #04 C, P1.2 A P1.3 P1.3 R4, LOOP 3 R4, #04 A R4, LOOP 4 R3, A P1.4
COMMENTS DIN word for LTC1288 Make sure CS is high CS goes low Load counter Rotate DIN bit into Carry SCLK goes low Output DIN bit to LTC1288 SCLK goes high Next bit Bit 2 becomes an input SCLK goes low Load counter Read data bit into Carry Rotate data bit into Acc. SCLK goes high SCLK goes low Next bit Store MSBs in R2 Clear Acc. Load counter Read data bit into Carry Rotate data bit into Acc. SCLK goes high SCLK goes low Next bit Load counter Rotate right into Acc. Next Rotate Store LSBs in R3 CS goes high
LOOP 1
LOOP 2
LOOP 3
8051
LOOP 4
MSBF BIT LATCHED INTO LTC1288
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
LTC1288 SENDS A/D RESULT BACK TO 8051 P1.2 LTC1288 TAKES CONTROL OF DATA LINE ON 4TH FALLING CLK
LTC1285/88 * TA07
LTC1285/LTC1288
TYPICAL APPLICATIONS N
A "Quick Look" Circuit for the LTC1285 Users can get a quick look at the function and timing of the LT1285 by using the following simple circuit (Figure 13). VREF is tied to VCC. VIN is applied to the +IN input and the -IN input is tied to the ground. CS is driven at 1/16 the clock rate by the 74C161 and DOUT outputs the data. The output data from the DOUT pin can be viewed on an oscilloscope that is set up to trigger on the falling edge of CS (Figure 14). Note the LSB data is partially clocked out before CS goes high.
4.7F 2.7V
BATTERY MONITOR INPUT 8V TO 16V 2.7V
VREF VIN +IN
VCC CLK
LTC1285 -IN DOUT GND CS
CLOCK IN 120kHz
LTC1285/88 * F15
TO OSCILLOSCOPE
Figure 13. "Quick Look" Circuit for the LTC1285
NULL BIT
LSB MSB (B0) (B11) VERTICAL: 2V/DIV HORIZONTAL: 20s/DIV
Figure 14. Scope Trace the LTC1285 "Quick Look" Circuit Showing A/D Output 101010101010 (AAAHEX)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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Micropower Battery Voltage Monitor A common problem in battery systems is battery voltage monitoring. This circuit monitors the 10 cell stack of NiCad or NiMH batteries found in laptop computers. It draws only 40A from the 2.7V supply at fSMPL = 0.1kHz and 30A to 62A from the battery. The 12-bits of resolution of the LTC1285 are positioned over the desired range of 8V to 16V. This is easily accomplished by using the ADC's differential inputs. Tying the -input to the reference gives an ADC input span of VREF to 2VREF (1.2V to 2.4V). The resistor divider then scales the input voltage for 8V to 16V.
CLR VCC CLK RC A QA B QB 74HC161 C QC D QD P T GND LOAD
0.1F 220k 39k +IN VCC LTC1285 -IN 39k 1F LT1004-1.2 3 VREF GND CS CLK DOUT
LTC1285/88 * F13
Figure 15. Micropower Battery Voltage Monitor
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LTC1285/LTC1288
PACKAGE DESCRIPTION
0.300 - 0.325 (7.620 - 8.255)
0.009 - 0.015 (0.229 - 0.381)
0.065 (1.651) TYP 0.005 (0.127) MIN 0.100 0.010 (2.540 0.254) 0.125 (3.175) MIN 0.018 0.003 (0.457 0.076) 0.015 (0.380) MIN
(
+0.025 0.325 -0.015 8.255 +0.635 -0.381
)
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
0.010 - 0.020 x 45 (0.254 - 0.508) 0.008 - 0.010 (0.203 - 0.254) 0- 8 TYP
0.053 - 0.069 (1.346 - 1.752)
0.016 - 0.050 0.406 - 1.270
0.014 - 0.019 (0.355 - 0.483)
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
RELATED PARTS
PART NUMBER LTC1096/LTC1098 LTC1196/LTC1198 LTC1282 LTC1289 LTC1522 DESCRIPTION 8-Pin SOIC, Micropower 8-Bit ADC 8-Pin SOIC, 1Msps 8-bit ADC 3V High Speed Parallel 12-Bit ADC Multiplexed 3V, 1A 12-Bit ADC 16-Pin SOIC, 3V Micropower 12-Bit ADC COMMENTS Low Power, Small Size, Low Cost Low Power, Small Size, Low Cost Complete, VREF, CLK, Sample-and-Hold, 140ksps 8-Channel, 12-Bit Serial I/O 4-Channel, 12-Bit Serial I/O
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7487
(408) 432-1900 q FAX: (408) 434-0507 q TELEX: 499-3977
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Dimensions in inches (millimeters) unless otherwise noted. N8 Package 8-Lead Plastic DIP
0.400* (10.160) MAX 8 7 6 5
0.045 - 0.065 (1.143 - 1.651)
0.130 0.005 (3.302 0.127)
0.255 0.015* (6.477 0.381)
1
2
3
4
N8 0695
S8 Package 8-Lead Plastic SOIC
0.189 - 0.197* (4.801 - 5.004) 0.004 - 0.010 (0.101 - 0.254) 8 7 6 5
0.050 (1.270) BSC
0.228 - 0.244 (5.791 - 6.197)
0.150 - 0.157** (3.810 - 3.988)
1
2
3
4
SO8 0695
LT/GP 0894 10K * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 1994

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